The invention concerns a process to transmit the refresh signal to a semiconductor memory that is connected to a central computer bus with a certain transmission priority, where the refresh signal and a refresh repeat signal that determines the chronological transmission of the refresh signal are generated by a central processing unit (CPU) and can be transmitted to the semiconductor memory via the central computer bus at a certain priority with respect to other aggregates that are connected to the computer bus.
An initially cited process and a circuit for this purpose are used for digital computer systems. With semiconductor memories used in these computer systems a refresh signal must be transmitted to the semiconductor memory in precisely defined cycles (refresh repeat cycles) to prevent it from losing its information. According to the specifications of a semiconductor memory it may be required, for example, that a refresh repeat signal be generated 128 times in a span of 2 milliseconds. This refresh repeat signal will then have a duration of about 15 microseconds.
In the chronological course of this refresh repeat signal at least one refresh signal of about 0.3 microsecond duration must occur, which is transmitted to the memory to prevent information contained in the memory from being lost. It does not matter in what region within the course the refresh repeat signal the refresh signal is transmitted to the semiconductor memory. What is important is that at least one refresh signal is transmitted to the semiconductor memory within one refresh repeat signal. The refresh signal, which leaves the CPU and is placed on the semiconductor memory via the computer bus, immediately starts a refresh cycle in the semiconductor memory which consists of a complex sequence of different signals.
In a first known embodiment the refresh signal is generated internally in the semiconductor memory, which naturally results in complicated circuitry and difficulties with synchronization between other aggregates of the computer and this semiconductor memory.
In another known embodiment the refresh repeat signal and the refresh signal which occurs in the course of the refresh repeat signal are generated by the central processing unit (CPU) and these are transmitted via the central computer bus to the semiconductor memory which is also connected to the computer bus. But there are other aggregates attached to the computer bus which want to transmit their data to the storage units or the CPU via the computer bus in accordance with their preceding controllers. This therefore creates priority and transmission problems (collisions) with computer bus access, if the CPU wants to transmit its refresh signal to the memory while the external units also want to transmit their data over the computer bus.
As a rule the CPU is assigned the lowest priority and the controllers, which switch disk or tape data onto the computer bus, are assigned the highest priority. No data processing takes place in the CPU such that, during processing and transmission over the computer bus, data are irretrievably lost, while this is the case with the transmission from magnetic tape or disk data onto the computer bus, unless the cited aggregates have the highest priority.
The problem arises what priority to assign the semiconductor memories connected to the computer bus, in order to avoid collisions with higher priority controllers of external mass storage units.
To date the procedure has been to assign the semiconductor memory the highest priority in the data bus, so that this semiconductor memory will perform its refresh cycle in any case, which naturally had the disadvantage that while the refresh signal was on the computer bus the external mass storage units were unable to transmit their signals over the computer bus, resulting in difficulties with data transmission or even data loss.
The invention has made it its task to develop a process for the transmission of the refresh signal onto the computer bus and a corresponding circuit in such a way that the external mass storage units can be assigned a higher priority than the refresh signal, which is generated by the CPU and is transmitted to the semiconductor memory via the computer bus. It is therefore the purpose of the present invention to improve the data flow of external mass storage units over the computer bus without interrupting this data flow with an intervening refresh signal.
To solve the posed problem the invention is characterized in that the refresh repeat signal is split into one or more chronologically successive component signals and that the transmission of the refresh signal onto the computer bus takes place at a low priority during the duration of the first component signal and that, in case transmission of the refresh signal is not possible during the duration of the first component signal, the refresh signal is assigned a higher priority and is placed on the computer bus with a higher priority during the course of another component signal which occurs chronologically after the first component signal.
An essential characteristic of the present invention, therefore, is a chronologically differentiated priority control of the refresh signal.
In a first sequence phase (occurrence of the first component signal) the refresh signal is assigned a relatively low priority, and it is attempted to place the refresh signal onto the computer bus with this low priority. If the computer bus happens to be free during the course of the first component signal, transmission of the refresh signal from the CPU to the semiconductor memory succeeds and the problem is solved, since, if free time is found on the computer bus then the external mass storage units are not transmitting data on the computer bus and there will be no collisions between the external mass storage units and the CPU which wants to transmit its refresh signal to the semiconductor memory. But if no "window" (i.e. a chronological gap) is found for the CPU to transmit its refresh signal to the semiconductor memory during the course of the first component signal, time becomes pressing, since one refresh signal must definitely be transmitted over the computer bus to the semiconductor memory within one refresh repeat signal. If during the course of the first component signal, therefore, no such free window was found, one must create such a window during the course of the other component signal which follows chronologically after the first component signal, in order to provide the semiconductor memory with its refresh signal.
One could give the CPU the highest priority of all aggregates connected to the computer bus for transmission of the refresh signal. This would offer the advantage that during the course of the second component signal (i.e. during the remainder of the course of the refresh repeat signal) the refresh signal would be certain to be transmitted to the semiconductor memory via the computer bus.
But the disadvantage is that the controllers of the external mass storage units will have problems with their data transmission over the computer bus, which applies particularly to disk storage, because of its high data density.